Vol. 3 No. 1 (2025): SJESR - March 2025
Articles

Proposed low Xilinx FPGA power consumption for recursive NOMA applied in optical visible light communication

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  • Sameer Sami Hassan Al-Obaidi
Sameer Sami Hassan Al-Obaidi Collage of Education for Pure Science/Ibn Al-Haitham, University of Baghdad, Baghdad, Iraq

Published 2025-03-30

Keywords

  • Visible Light Communication,
  • NOMA,
  • Kintex-7,
  • AMD Xilinx,
  • FPGA Power estimation

Copyright (c) 2025 Samarra Journal of Engineering Science and Research

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

Proposed low Xilinx FPGA power consumption for recursive NOMA applied in optical visible light communication. (2025). Samarra Journal of Engineering Science and Research, 3(1), 21-33. https://doi.org/10.65115/m5sr5a87

Abstract

Today the NOMA has exponential growth in the use of Optical Visible Light Communication (OVLC) due to good features such as high spectral efficiency, low BER, and flexibility. Moreover, it creates a huge demand for electronic devices with high-speed processing and data rates, which leads to more FPGA power consumption. Therefore; it is a big challenge for scientists and researchers today to recover this problem by reducing the FPGA power and size of the devices. The subject matter of this article is producing an algorithm model to reduce the power consumption of (Field Programmable Gate Array) FPGA used in the design of the Non-Orthogonal Multiple Access (NOMA) techniques applied in (OVLC) systems combined with a blue laser. However, The power consumption comes from Complex Digital Signal Processing (DSP) due to mathematical operations such as addition and multiplication which consume more FPGA power when compared with other parts of NOMA. The multiplication operation consumes more FPGA power than the additional operation. The article's goal is to propose low FPGA power consumption algorithms called recursive IFFT/FFT which reduce the FPGA power consumption by more than 45% compared with the model without the proposed algorithm using AMD Xilinx Kintex-7 with high-speed analogue card.

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